1. Field of the Invention
The disclosure relates in general to a three-dimensional (3D) semiconductor device, more particularly to a high speed vertical channel (VC) 3D semiconductor device.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed. Various semiconductor devices with three-dimensional (3D) stacked structures, having single-gate unit cells, double gate unit cells or surrounding gate unit cells, have been provided.
It is desirable to develop a semiconductor device with 3D stacked structure not only with larger number of multiple planes being stacked to achieve greater storage capacity, but also with memory cells having excellent electrical properties (such as reliability of data storage and speed of operation), so that the memory cells can be erased and programmed effectively. Typically, NAND Flash page size is proportional to the number of the bit lines (BL). Accordingly, when the device is scaled down, not only the decreased cost but also the increased read/write data rate are achieved due to the increasing of parallel operation, which leads to higher data rate. Typically, a 3D vertical channel (VC) semiconductor device have larger hole size to reduce the process challenge. However, larger cell size results in less bit line number, less parallel operation, and less speed of read/write data. For a conventional cell design, the cells arranged in the same row are selected by one selection line, and the cells arranged in the same column are corresponding to one bit line. Take 16 cell strings (arranged as 4 rows and 4 columns) with 4 BLs as example; each cell string corresponds to one BL and one selection line (such as SSL 1/2/3/4). To obtain all the dada in this example, it is required to select the SSL1 to get 4 strings data, then followed by selecting the SSL2, SSL 3 and SSL 4 to get the next 12 strings data. It needs 4 cycles of operation to get all of the strings data under SSL 1/2/3/4. Also, when the SSL1 is operated, the cell strings in the SSL 2/3/4 are also suffered from the same gate bias, thereby suffering from gate disturbance. Besides, the “non-selected strings” having the gate voltage means the unnecessary power consumption. Thus, the conventional cell design has not only low speed of operation, but also large power consumption and large disturbance.